Digital Logic Design and Functional Testing using Verilog HDL

1. (a) Write a parametric Verilog module for computing out=ax2+bx+c. “a”, “b”, and “c” are three 4-bit signed parameters with the default values of “a”= -4,“b”= 3, and “c”= -3. “x” is a WL-bit signed input. The output “out” is registered using the clock signal “CLK”. (b) Write a testbench for your design. Demonstrate the output waveform for the following test stimuli: 4’b1001, 4’b0001, and 4’b1111.
2. Write a parametric Verilog module for each of the following modules: (a) Instruction memory, (b) register file in the write-first mode, (c) data memory, and (d) arithmetic logic unit (ALU). Your instruction memory should be able to read a MIPS program from a .mem file and the data memory should be able to read the initial data from a .txt file. Your ALU should be able to support the following operations: addition, subtraction, logical left-shift, logical right-shift, logical variable shift-left, logical variable shift-right, arithmetic variable shift-right, and bitwise AND, OR, XOR, and XNOR logical operations. The details of these modules are described in the book. For example, the register file receives an active-high write enable signal “RFWE” and a clock signal “CLK”. On the positive edge of the clock CLK, the memory first writes the value on the input data port “RFWD” into the location addressed by “RFWA” if the “RFWE” is high and then reads the values from locations specified by the address ports “RFR1” and “RFR2” and places them on the output data port “RFRD1” and “RFRD2”. The memory size should be parametric and by default, it has 32 words and each word is 32 bits.
3. A combination lock has a reset input “RESET”, two inputs “b0” and “b1”, one for 0 and one for 1, respectively, and an unlock output “UNLOCK”. In reality, inputs are asynchronous signals, but assume that they are synchronous. (a) Draw the finite state machine for your design. Is this a Moore machine or a Mealy machine? (b) Write a Verilog module using a finite state machine (FSM) to simulate a combination lock that would unlock if the input sequence is 01001. (c) Write a testbench for your design. Present the output waveform of your design using the following input sequence “0001001011”. Include the input/output signals along with the state variable in the output waveforms.

Sample Solution