Draw a state diagram to represent the behaviour of the counter you are required to design. It is
suggested you employ the letters of the alphabet to refer to each state and keep the outputs as
decimal numbers at this stage.
Insert state diagram here. (2 marks)
Convert the state diagram into its associated state table.
Insert state table here. (2 marks)
Assume that a simple binary state variable allocation can be made and that any unused states can be
treated as don’t cares. Draw the corresponding transition table for the counter including flip-flop (DFF) inputs and BCD outputs for your designated storage device.
Insert transition table here. (4 marks)
Using excitation maps (K-maps) to determine the next state logic functions that can be used to drive
your flip-flop inputs.
Insert excitation maps clearly showing groups and logic functions here. (6 marks)
Also draw Karnaugh maps to deduce minimal logic functions for the 4 output functions that are
required to give the BCD output codes. Note that depending on your ID number not all outputs will
be significant in all cases.
Insert the output function maps and logic equations here. (5 marks)
Enter the associated schematic circuit diagram here along with commentary. The simulation
results clearly show the implementation is fully compliant with the specification. (6 marks)
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