EXPONENTIAL SOURCE
Real digital waveforms exponentially rise and
fall, so it is best to be represented by an
exponential source.
VIN source connected between node in and gnd. Initial value
is 0, final value is 1.2V. There is an initial delay of 0 sec. At
t=0 it starts to rise with a rise time constant tr of 50 ps
(meaning around 5tr or 250ps, it reaches full value of 1.2V). Then at 1 ns, it starts to fall with a fall time constant of 50 ps) Before the assignment, some theory first!! If you want just a saturated exponential function e.g. 1.2(1-e -t/tr) 1.2V There is a trick we can use: We can let “the time it starts to fall” to be very large Let’s say our transient analysis ends at 2 ns .TRAN 10p 2n We selected 1 sec for the time it starts to fall. I= Imax(e -t- e -t ) This current source is hard to model in HSpice therefore, we chose to represent this using two parallel current sources that are saturated exponentials in other words: I=Imax(1-e -t ) - Imax(1-e -t) CURRENT SOURCE REPRESENTATION FOR PARTICLE STRIKE. Imax is simply obtained by Q/ (t- t) Take t = 100 ps, and t = 5 ps Directions are shown for a PMOS hit (sometimes 1 ps) Iseu1 0 VO1 EXP(0 0.10m 0p 5p 5 5) Iseu2 VO1 0 EXP(0 0.10m 0p 100p 5 5) Assume we want to represent an SE hit on PMOS that is 10 fC: Imax =Q/ (t- t)≈ 0.1 mA The initial timing is set at 0p and can be changed depending on the need (such as soft delay simulation etc.) t = 100 ps, and t = 5 ps HSpice Simulation Problems Assume first inverter is 2x and the remaining are 1x (min size) inverters in 32 nm technology.. For SEU current pulse use double exponential waveform which is given as I= Q/( t-t)(e -t- e -t
)… Select t=100ps t=5ps. Choose a 15 fC charge
for the SEU pulse and obtain the printouts for pulses on Vo1 Vo2 and Vo3. Note
you can determine the maximum value Imax of the current source from
Q/( t-t) in other words Imax.– see page 3 for more
1) 80 pts.
In the next step, you will apply the gate sizing method. For that, you
will need to size up the first inverter (increase transistor widths) until
the pulses cannot propagate thru 2nd and 3rd inverter. Increase the
sizing in 3x, 4x, 5x and so on until mitigation is obtained and record
that value.
If the pulses propagating at Vo3 is less then 100 mV, we assume the
sizing process is complete (since they are well below threshold)
Provide the plots on outputs and include the new size that you found.
For this assignment, provide the Hspice codes of each circuit.
For Question 1, these are what you will need to include:
a) Include the printouts for the waveforms at vicout and VOV2 before
sizing simulation. Also include the HSpice Code. Also include the
waveform at the strike location (output of aggressor driver)
b) In your report mention, the size of Victim driver, which mitigates the
SET transient.
c) Include the HSpice code and the printout of waveforms of vicout
and VOV2 after doing the sizing simulation.
2) SE Crosstalk Noise Simulation: Hspice - 120 pts
Assume we have an aggressor and victim line that is coupled with
coupling capacitance.
Take victim and aggressor line resistance as 400 ohms each and take
ground capacitances as 20 fF. The coupling capacitance value is 110
fC.
Obtain 8- model (Note the class example was for 10 pi) for both the
aggressor and victim line and distribute the coupling capacitance as
shown in class. (in 8 pi, middle capacitors have 1/8 th of total and the
one on edges have 1/16 times the total), wire resistance is 1/8th
always
Finally obtain the circuit shown on next page.
Assume a 150 fC deposited charge. This has to be represented by
current source. Find current source representation for this charge
and include it in the circuit. (see next page)
vicout
Assume aggressor driver (inverter A) is 2x and the remaining are 1x
(min size) inverters in 65 nm technology. Use model cards for
transistor given in Predictive Technology Web site for 65 nm (choose
the 2002 version of 65 nm). Also, take VDD as 1.2 V in your
simulations
Cc9
Observe the waveforms at vicout and VOV2 and obtain the screenshot
pictures before sizing (to be included with report).
If waveform showing on VOV2 (something more than half VDD or 0.6),
then you are going to be needing driver sizing on victim driver (Inverter B)
Determine size of Inverter B, which will reduce VOV2 to
almost zero or close. Increase sizing in multiples of 1x.
Sample Solution