The Verilog Codes

1) Design a digital circuit by writing the Verilog Codes based on following specifications.
There are 5 inputs, v, w, x, y and z that represent grade of 5 products inside a box. Each of the
inputs is 8-bit. The grade of the product is according to the number of “0” in the 8-bit input as
follows:-
7- 8 : A
5-6: B
3-4 : C
0-2 : D
An output out represents the category of that box based on following conditions :-
If total number of product with grade A is the highest, out = 0
If total number of product with grade B is the highest, out = 1
If total number of product with grade C is the highest, out = 2
If total number of product with grade D is the highest, out = 3

  • Resolve ties by choosing the higher grade.
    Example
    v = 00000001, w = 00000000, x = 00011111, y = 01010101, z = 00100000 : out = 0
    v = 10100000, w = 10110100, x = 00000111, y = 01101011, z = 00001000 : out = 1
    v = 11001110, w = 01101010, x = 01111000, y = 01111111, z = 00110111 : out = 2
    v = 11111111, w = 11011111, x = 11101101, y = 11111101, z = 01111111 : out = 3
    v = 01101101, w = 11111111, x = 11111111, y = 00000000, z = 11011101 : out = 3
    You have to use the concept of connection of instances for the top level module and procedural
    constructs/connection of instances for low level modules. Top level module only consists of multiple
    low level modules.
    You need to verify the designed circuit by writing test bench for it and simulate using ModelSim. No
    need to test all combinations.

2) Design a digital circuit by writing the Verilog Codes based on following specifications.
i) An input in is between 0 to 15 and it will be inserted to the circuit one for each clock cycle.
ii) An output out will be based on the following conditions
If majority of the input in for the last five clock cycles are an even number, out is the maximum
number of in for the last five clock cycles
If majority of the input in for the last five clock cycles are an odd number, out is the minimum
number of in for the last five clock cycles
iii) The circuit is positive edge triggered and synchronous reset. The circuit starts to process the input
signal in based on positive edge triggered and also when the rst is equal to 0. Assume that the input
signal in is available at every clock cycle.
You may refer to figure 1 for an example of the waveform for the above circuit. You have to use the
concept of procedural constructs. Needs to verify the designed circuit through simulation

Sample Solution

ACED ESSAYS